Variable clocking in an embedded symmetric multiprocessor system

摘要

In multiprocessor systems the task of holding power dissipation to its lowest possible level is challenging. This invention permits reduced power dissipation by optionally clocking selected central processing units at lower frequencies if they are not fully loaded. The variable clocking system enables synchronization between central processing units operating a differing frequencies and shared memory and peripherals. This allows for significant power reduction in the frequently occurring scenario where all processors are not driven to their limits by prevailing system requirements.