发明名称 |
Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment |
摘要 |
A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a semiconductor layer on an insulating layer. In the MOS transistor having a source tied body structure, a semiconductor regions having a low impurity concentration is formed between a regions for extracting excessive carriers and source/drain regions. Thus, the breakdown voltage at the junctions between the extracting regions and the source/drain regions is increased and a parasitic bipolar effect is suppressed without breakdown between the extracting regions and the source/drain regions.
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申请公布号 |
US2003116801(A1) |
申请公布日期 |
2003.06.26 |
申请号 |
US20020309168 |
申请日期 |
2002.12.04 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
YAMAZAKI YASUSHI |
分类号 |
G02F1/136;G02F1/1368;G09F9/30;H01L21/336;H01L21/82;H01L27/118;H01L27/12;H01L29/786;H04N9/31;(IPC1-7):H01L29/76 |
主分类号 |
G02F1/136 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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