发明名称 |
SERIAL LINK ARCHITECTURE |
摘要 |
A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL) , a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker. |
申请公布号 |
WO02057924(A3) |
申请公布日期 |
2003.06.26 |
申请号 |
WO2002GB00123 |
申请日期 |
2002.01.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED |
发明人 |
CRANFORD, HAYDEN, CLAVIE;NORMAN, VERNON, ROBERTS;SCHMATZ, MARTIN, LEO |
分类号 |
H03L7/08;H03L7/095;H03L7/099;H03L7/10;H04L7/033;H04L27/00 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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