发明名称 System and method for employing a global bit for page sharing in a linear-addressed cache
摘要 A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.
申请公布号 US2003120892(A1) 申请公布日期 2003.06.26
申请号 US20030366200 申请日期 2003.02.12
申请人 INTEL CORP 发明人 HUM HERBERT H J;JOURDAN STEPHAN J;MARR DEBORAH;HAMMARLUND PER H
分类号 G06F12/10;(IPC1-7):G06F12/00 主分类号 G06F12/10
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