发明名称 PROCESSING BUFFERED DATA
摘要 <p>Data reception apparatus for receiving and processing a data stream including a stream of data units, the data apparatus comprising: a buffer; a data reception controller for receiving data units from the data stream, storing received data units in the buffer, and if the amount of data from the data stream that is stored in the buffer exceeds a predetermined amount, generating a buffer load interrupt for the data stream; and a processor responsive to the buffer load interrupt to: a) disable handling of further buffer load interrupts for the data stream; and b) repeatedly activate a routine to process a single data unit from the data stream that is stored in the buffer until all the data units in the buffer have been processed and then reset the buffer.</p>
申请公布号 EP1320990(A1) 申请公布日期 2003.06.25
申请号 EP20010967527 申请日期 2001.09.19
申请人 STMICROELECTRONICS, LTD. 发明人 HAYDOCK, STEVEN
分类号 H04N5/00;(IPC1-7):H04N5/00 主分类号 H04N5/00
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