| 摘要 |
PURPOSE: A device and a method for expanding a memory bus are provided to alternatively latch N/2-byte data from one memory, so as to access N-bit data corresponding to a data bus of a CPU through one access time. CONSTITUTION: A CPU(210) outputs address signals, address strobes, upper data strobes and lower data strobes, and reads 16-bit data by a data acknowledgement signal. A memory(220) outputs 8-bit data by an expansion address signal(XADDR), a chip selection signal(/CSRAM) for reading address signals(ADDR(1¯23)) and upper/lower data. And a controller(230) reads the upper/lower data of the memory(220) twice by the 8 bit, and delivers the read data to the CPU(210) with 16-bit. In the controller(230), an expansion address generator(231) receives the address signals, the address strobes, the upper data strobes and the lower data strobes from the CPU(210), to generate the expansion address signal(XADDR) for designating the upper data and the lower data. An address decoder(232) reads the address signals to output the chip selection signal(/CSRAM). A data acknowledgement signal generator(233) outputs the data acknowledgement signal to the CPU(210) to secure a response speed of the memory(220). And an expansion data interface(234) latches the data read twice by the 8 bit from the memory(220) to an internal register, to output a 16 bit value to a data bus.
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