| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of decrease the depth of a logic metal contact hole and easily filling the logic metal contact hole by simultaneously forming the logic metal contact while forming a DRAM(Dynamic Random Access Memory) cell lower electrode. CONSTITUTION: A lower electrode formation region and logic analog capacitor formation region is opened and a DRAM cell storage node contact hole is formed at the sixth ILD(InterLayer Dielectric) deposited structure by using a dual damascene process. After sequentially depositing lower electrode material(86) and the seventh ILD on the resultant structure, a CMP(Chemical Mechanical Polishing) process is carried out on the seventh ILD. After carrying out a photolithography and wet etching process, a logic analog capacitor insulating layer(89) is deposited on the resultant structure. A plurality of upper electrodes(90,91) are formed by depositing and patterning the eighth ILD. Then, a plurality of metal lines(94,95,96) are formed at the resultant structure.
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