发明名称 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving etch profile when forming SAC(Self Align Contact) by using an APL(Advanced Planarization Layer). CONSTITUTION: A plurality of conductive patterns are formed on a substrate(10). A spacer insulating layer(14) is formed on the resultant structure. A TEOS layer(15) is formed on the spacer insulating layer(14). An advanced planarization layer(16) is formed on the TEOS layer. A contact hole is then formed to expose the surface of the substrate(10) between the conductive patterns by selectively etching the advanced planarization layer(16), the TEOS layer(15) and the spacer insulating layer(14).
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申请公布号 |
KR20030049126(A) |
申请公布日期 |
2003.06.25 |
申请号 |
KR20010079248 |
申请日期 |
2001.12.14 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
HWANG, CHANG YEON;KIM, SANG IK;LEE, MIN SEOK;LEE, SEONG GWON;SEO, WON JUN |
分类号 |
H01L21/3205;(IPC1-7):H01L21/320 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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