High speed differential data sampling circuit

摘要

A differential data sampling circuit is provided for sampling an input signal line with precise timing so as to provide reduced sensitivity to noise. The differential data sampling circuit includes a latch circuit for initially sampling a differential data signal in response to a first strobe signal. The latch circuit operates to rapidly capture the signal level present on the input signal line. The output of the latch circuit is then sampled by a strobe circuit in order to capture and hold the output of the latch circuit based on a second strobe signal. In preferred embodiments, the latch circuit has a high input impedance. A digital data receiver including such a differential data sampling circuit is also provided.