| 摘要 |
PURPOSE: A wafer burn-in test mode circuit is provided to support various items of a test by receiving one address and decoding outputs of each terminal of plural shift registers to minimize the number of addresses necessary for a decoding process. CONSTITUTION: A wafer burn-in test mode circuit includes a command decoder(201), an address latch(102), a register(206), a wafer burn-in test mode entry circuit(205), a plurality of shift registers(212-215), a wafer burn-in test priority decision circuit(211), a decoder(210). The command decoder outputs a plurality of command signals to drive a semiconductor memory device. The address latch receives and latched a plurality of address signals. The register is used for storing one wafer burn-in address signal according to the command signal of the command decoder. The wafer burn-in test mode entry circuit receives a wafer burn-in address signal and generates a wafer burn-in test mode entry signal. The shift registers are used for shifting the wafer burn-in address signal. The wafer burn-in test priority decision circuit outputs a test priority signal to perform sequentially a test. The decoder outputs a wafer burn-in test signal by decoding output signals of the shift registers according to the test priority signal.
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