发明名称 METHOD OF FORMING SHALLOW TRENCH ISOLATION IN SILICON
摘要 A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches are then filled with an insulative material, such as oxide.
申请公布号 KR20030051805(A) 申请公布日期 2003.06.25
申请号 KR20037006404 申请日期 2003.05.12
申请人 发明人
分类号 H01L21/76;H01L21/762 主分类号 H01L21/76
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