| 摘要 |
PURPOSE: An output buffer circuit is provided to reduce a swing time of a data signal and improve a data output speed by reducing a required time of an output terminal for intermediate electric potential. CONSTITUTION: An output buffer circuit includes the first logic portion(21), the second logic portion(22), the first switching portion(P20), the second switching portion(N20), a load portion(23), and a coercive electric potential portion(24). The first logic portion performs a logical operation for an output enable signal and a data signal. The second logic portion performs a logical operation for an inverse signal of the output enable signal and a data signal. The first switching portion controls the electric potential of an output terminal according to an output signal of the first logic portion. The second switching portion controls the electric potential of the output terminal according to an output signal of the second logic portion. The load portion maintains the electric potential of the output terminal to the predetermined electric potential. The coercive electric potential portion maintains the electric potential of the output terminal according to the output enable signal to the predetermined electric potential.
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