| 摘要 |
PURPOSE: A reset circuit is provided to make a watch dog timer continuously detect whether an overflow occurs at a system, and to stop the system if the overflow occurs at the system so that it can reduce a power and prevent system damage. CONSTITUTION: The circuit comprises a watch dog timer(21), a reset signal generator(22), a system initialization and restart module(23), a counter(24), an AND gate(25), and a system stop module(26). The watch dog timer(21) senses a system operation time, and generates an overflow signal when an error occurs at a system. The reset signal generator(22) receives the overflow signal from the watch dog timer(21) and generates a system reset signal. The system initialization and restart module(23) receives the system rest signal from the reset signal generator(22), resets the system and initializes the system. The counter(24) counts the overflow signal generated at the watch dog timer(21). The AND gate(25) combines the reset signal of the reset signal generator(22) with the output signal of the counter(24), and generates a system stop signal. The system stop module(25) receives the system stop signal from the AND gate(24), and stops the system.
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