| 摘要 |
PURPOSE: A programmable logic circuit is provided to offer an effective data interface between a microprocessor and a peripheral circuit in a case that the clock speed of the microprocessor is different from that of the peripheral circuit. CONSTITUTION: The circuit comprises a flipflop(51), the first buffer(56), the second buffer(57), the first logical summation element(52), the second logical summation element(53), the first inverter(54), and the second inverter(55). The flipflop(51) latches the data transmitted from a microprocessor for synchronizing the data with a minimum clock conversion time of a peripheral circuit, and then outputs the data to the peripheral circuit. The first buffer(56), installed between the flipflop(51) and the peripheral circuit, buffers the output of the flipflop(51), and outputs the buffered data to the peripheral circuit if the first enable signal is input. The second buffer(57) buffers the output data of the peripheral circuit, and outputs the buffered data to the microprocessor if the second enable signal is input. The first logical summation element(52) logically sums the reset data and the direction instruction data output by the microprocessor, and outputs the summation result as the first enable signal. The second logical summation element(53) logically sums the reset data, the inverted value of the direction instruction data, and the inverted value of the clock data, output by the microprocessor, and outputs the summation result as the second enable signal. The first inverter(54) inverts the direction instruction data, and the second inverter(55) inverts the clock data.
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