| 摘要 |
PURPOSE: A delay locked loop is provided to improve a data access time by reducing a variation of width of data outputted from a semiconductor device. CONSTITUTION: A delay model(200) receives an external clock and monitors a delay time of an internal circuit. The first and the second delay lines(700,600) delay the external clocks during a predetermined time. A shift register(400) controls the delay time of the first and the second delay lines(700,600). A phase comparator(300) outputs a phase locking signal or a phase increase and decrease signal according to a phase difference between the external clock as the reference clock and a comparative clock of the delay model(200). A fine delay controller(100) stores the phase increase and decrease signal, outputs a phase of the comparative clock to the phase comparator(300), and controls the shift register(400) by comparing the phase increase and decrease signal of the phase comparator(300) with the stored phase increase and decrease signal.
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