| 摘要 |
PURPOSE: A clock converter circuit is provided to prevent an irregular variation of pulse width by fixing a current clock and counting a varied clock to convert a clock state of fixing output to a clock state of release output under a low level. CONSTITUTION: A register portion(51) outputs a clock conversion signal. A timing control portion(52) includes the first RS latch block for outputting a clock selection signal, the first clock fixing signal output portion for outputting a clock conversion fixing signal, the second clock fixing signal output portion for outputting a clock selection fixing signal, and the second RS latch block for outputting a clock conversion release signal. A clock selection portion(53) includes the first MUX for outputting selectively the first and the second clock signals according to the clock selection signal and the second MUX for outputting selectively the first and the second clock signals according to the clock conversion signal. A varied clock counter portion(55) counts an output clock of the second MUX and an inverse clock according to the clock conversion release signal. A clock output portion(54) outputs one of the first and the second clock signals from a low level.
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