| 摘要 |
PURPOSE: A method for fabricating a short channel transistor of a semiconductor device is provided to reduce a short channel effect and drain induced barrier lowering by forming a low doped drain implantation region slightly separated from a channel region of the transistor. CONSTITUTION: After the first oxide layer, the first nitride layer, the second oxide layer and the second nitride layer are sequentially deposited on a semiconductor substrate(1), a pattern is formed by using the first mask. The second-a nitride layer and the second-a oxide layer are formed on the resultant structure, the first spacer layer is deposited and the first spacer is formed through a blanket etch process. While the first spacer is formed, the first-a oxide layer is formed through a wet etch process after the first-a nitride layer is formed. A gate insulation layer is formed on the exposed semiconductor substrate. A gate conductor(13) is formed through a chemical mechanical polishing(CMP) process using the second-a nitride layer as a CMP stop layer. The second-a nitride layer, the first spacer, the second-a oxide layer and the first-a nitride layer are removed through a wet etch process. After a low doped drain implant(15) is formed on the resultant structure and the second spacer layer is deposited, the second spacer(17) is formed through a blanket etch method. After a source/drain region(19) is formed, the first-a oxide layer is removed through a wet etch method. A salicide layer(21) is formed on the gate conductor and the source/drain region. |
