发明名称 |
Reduced cost, high speed circuit test arrangement |
摘要 |
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester. |
申请公布号 |
US6583639(B1) |
申请公布日期 |
2003.06.24 |
申请号 |
US20000633305 |
申请日期 |
2000.08.08 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
VOGLEY WILBUR C. |
分类号 |
G01R31/319;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/319 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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