发明名称 Shared cache structure for temporal and non-temporal instructions
摘要 A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
申请公布号 US6584547(B2) 申请公布日期 2003.06.24
申请号 US20010803357 申请日期 2001.03.09
申请人 INTEL CORPORATION 发明人 PALANCA SALVADOR;COORAY NIRANJAN L.;NARANG ANGAD;PENTKOVSKI VLADIMIR;TSAI STEVE;ABDALLAH MOHAMMAD
分类号 G06F12/08;G06F12/12;(IPC1-7):G06F12/00 主分类号 G06F12/08
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