发明名称 |
Semiconductor memory device having intermediate voltage generating circuit |
摘要 |
In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is applied to the reference node with a tester driver via the pad to control a potential of an output node in an output stage. Thus, the semiconductor memory device is capable of stably controlling the bit line reference potential VBL regardless of the drivability of the tester driver during the device evaluation test.
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申请公布号 |
US6584020(B2) |
申请公布日期 |
2003.06.24 |
申请号 |
US20010909967 |
申请日期 |
2001.07.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMAUCHI TADAAKI;MUNEYASU MAKOTO |
分类号 |
G11C11/401;G11C5/14;G11C7/12;G11C29/12;(IPC1-7):G11C16/04 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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