| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance the integration degree of a semiconductor device in which a plurality of circuits that are substantially identical are arranged repeatedly like memory cells. <P>SOLUTION: Each of a plurality of repeated units includes a plurality of memory cells. The second conductivity type well is formed across a plurality of repeated units on the top layer part of a semiconductor substrate. The first conductive channel MOS transistors in a plurality of repeated units are arranged in the second conductivity type well. The second conductivity type well tap region is formed in the second conductivity type well of a part of memory cell included in the repeated units. Interlayer connecting members are arranged in the memory cell that is identical or adjacent to the memory cell in which the second conductivity type well tap region is arranged. The interlayer connecting member is connected with the source region of the first conductivity type channel MOS transistor and the second conductivity type well tap region. <P>COPYRIGHT: (C)2003,JPO |
