| 摘要 |
PROBLEM TO BE SOLVED: To sufficiently save the power of the programmable logical circuit as a whole or reduce the calorific value of the whole circuit while maintaining the processing rate of the circuit without generating a clock skew. SOLUTION: The programmable logical circuit is provided with a plurality of logical blocks for executing logical processing, wirings 2 for connecting respective logical blocks 1, a wiring changing means 3 capable of setting up and changing the wiring state of the wirings 2 by a program, a clock net 4 independent from the wirings 2 in order to supply a clock signal for applying operation timing to respective logical blocks 1, and clock control means 5, 5-1 to 5-5 for dynamically controlling the switching of supply/stop of a clock signal to respective logical blocks 1 so as to stop the supply of the clock signal to a non-driven logical block 1 out of these logical blocks 1. COPYRIGHT: (C)2003,JPO
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