PHASE-LOCKED LOOP (PLL) CIRCUIT FOR SELECTIVELY CORRECTING CLOCK SKEW IN DIFFERENT MODES

摘要

A phase-locked loop (PLL) circuit (100) includes multiple selectable feedbac k and a mode selector (160) for selecting different feedback paths in differen t operating modes. The PLL circuit (100) corrects for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.