| 摘要 |
The invention discloses a delay clock pulse-width adjusting circuit. The circuit comprises: a power supply; a delay comparator, which one input terminal inputs a sine wave signal and another input terminal inputs a compare voltage, which output terminal outputs a clock signal with a defined duty-ratio; and a converting circuit, converting the clock signal to a DC level, which input terminal is connected to the output terminal of the delay comparator, which output terminal is connected to the another input terminal of the delay comparator. With the circuit, the duty-ratio of a clock signal is no larger abrupt change, so burden of the digital signal processing is decreased. Consequently, the adjusting circuit satisfies requirements: high traffic, low error rate and high stability of the clock signal duty-ratio. |
