SUPERCHARGE MESSAGE EXCHANGER

摘要

A system with a first random access memory (RAM), a second RAM (108A-108B), a first processor(114A) coupled to the first RAM(108A) and a second processor(108B) coupled to the second RAM. The first RAM (108A) is configured to store input/output (I/O) completions from at least two engines(102A,104A). The second RAM(108B) is also configured to store I/O completions from at least two other engines (102B, 04B). When all engines are active, the system writes I/O completions from the engines to the first and second RAMs (108A,108B). The first processor (114A) processes I/O completions stored in teh first RAM (108A). The second processor(114B) processes I/O completions stored in the second RAM (108A).