Memory cell with trench transistor

摘要

The trench depth is optimized in such a way that the locations for electron and hole injections into the storage layer (11), which is disposed in boundary layers (10, 12) between the trench walls and the gate electrode (4), coincide. The junctions (14) at which the doping of the source zone (2) and the drain zone (3) changes into the opposite sign (i.e. that of the conductivity type of the semiconductor body (1)) and which border the channel region (5) abut a curved region of the trench bottom (7) or a curved lower region of the lateral trench walls (6, 8).