| 摘要 |
A fail analysis device enabling a simplified operation and a reduced operation time. A reduced data acquiring section ( 40 ) reads a reduced logical data, obtained by reducing detailed logical data as a test result, from a CFM ( 120 ) in a semiconductor test device ( 100 ) and acquires it. A main viewer generating section ( 80 ) generates a main viewer window including a list of a test result for each DUT based on the reduced logical data for displaying on a display device ( 94 ). The list includes a result image indicating a pass/fail for each DUT and the reduced image of a fail bit map.
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