| 摘要 |
A system and method is provided of placing components on a chip for performing a function in order to minimize wire length and wire congestion. In a preferred embodiment of the present invention, a plurality of components, which are adapted to receive a plurality of bits, are arranged in lines that are substantially parallel to one another. Within each line, the components are arranged such that the component adapted to receive the least-significant bit ("LSB") for that line is positioned at a first end of the line, and a component adapted to receive the most-significant bit ("MSB") for that line is positioned at a second end of the line. The lines are then oriented such that the first end of all odd numbered lines are adjacent the second end of all even-numbered lines (i.e., in a serpentine fashion). The plurality of components are then electrically connected. In one embodiment of the present invention, each component is electrically connected to a next-least-significant component and a similarly-positioned component from the next-least-significant similarly-oriented line through a wire. In another embodiment of the present invention, each component is electrically connected to a next-most-significant component and a similarly-positioned component from the next-most-significant similarly-oriented line.
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