| 摘要 |
A frame buffer (100, 300) receives N asynchronous digital video signals and generates a data stream corresponding to a single video signal representing all of the N asynchronous video signals responsive to read and write memory addresses generated by a frame buffer controller (200, 400), where N is an integer greater than or equal to 2. If desired, N can be a positive integer equal to or greater than 4. Preferably, the frame buffer includes N dual ported memory devices (110, 120, 130, 140), each or which can be written to and read from simultaneously and independently. A VGA quad device and apparatuses incorporating same are also described.
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