发明名称 |
Apparatus for branch prediction |
摘要 |
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit, dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. On the other hand, an instruction memory stores a plurality of lines of a plurality of instructions, and a branch memory stores a plurality of branch prediction entriesd.
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申请公布号 |
EP1320031(A2) |
申请公布日期 |
2003.06.18 |
申请号 |
EP20030003266 |
申请日期 |
1994.12.15 |
申请人 |
MIPS TECHNOLOGIES, INC. (A DELAWARE CORPORATION);KABUSHIKI KAISHA TOSHIBA |
发明人 |
JOSHI, CHANDRA S.;RODMAN, PAUL;HSU, PETER YAN-TEK;NOFAL, MONICA R. |
分类号 |
G06F9/32;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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