发明名称 |
STRUCTURE OF DELTA SIGMA DIVIDER |
摘要 |
PURPOSE: A structure of a delta sigma divider is provided to obtain the capacity to synthesize the broadband frequency and maximize an effect of a delta sigma method by adding an output value of a delta sigma modulator to an external input value to modulate a value of a swallow counter. CONSTITUTION: A delta sigma modulator(41) is used for receiving a frequency and an external input value. A swallow adder block(40) is used for adding an external input value to an output value of the delta sigma modulator. A program register block(37) is used for storing an output value of the swallow adder block. A pulse swallow counter block(34) is formed with a dual modulus prescaler, a program counter, and a swallow counter in order to divide an input frequency according to a stored value of the program register block.
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申请公布号 |
KR20030047565(A) |
申请公布日期 |
2003.06.18 |
申请号 |
KR20010078268 |
申请日期 |
2001.12.11 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
CHOI, JANG HONG;HAN, SEON HO;JANG, JAE HONG;YOO, HYEON GYU |
分类号 |
H03L7/00;H03L7/197;H03M7/00;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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