Vorrichtung und Verfahren zur Fehlererkennung in einer integrierten Schaltung mit einer parallelen-seriellen Anschlussstelle

摘要

The integrated circuit incorporated a serialising circuit 109T at the exit and deserialising circuit 109R at the entry. The arrangement is such that an insertion buffer is provided at each of th exits connected to an EOR function with two entries. Each second entry receives information for transmission, constituting with the insertion information coming from the insertion buffer a substitution information. an extra buffer permits comparison of the sequence.