发明名称 Versatile time division multiple access slot assignment unit
摘要 The present invention is a versatile time division multiple access ("TDMA") slot allocation unit. In one embodiment, the versatile TDMA slot allocation unit includes a slot counter configured to provide an address representative of a time slot and a slot descriptor table that contains one or more slot descriptors each of which describes an action that may be performed within the time slot. The slot descriptor table is configured to receive the address and provide the slot descriptor pointed to by the address. In addition, the TDMA slot allocation unit includes a slot descriptor decoder configured to decode the slot descriptor and provide one or more signals.
申请公布号 US6580730(B1) 申请公布日期 2003.06.17
申请号 US20000624128 申请日期 2000.07.24
申请人 INTEL CORPORATION 发明人 LOUKIANOV DMITRIL
分类号 H04J3/16;H04L12/56;H04N7/173;H04Q11/04;(IPC1-7):H04J3/12 主分类号 H04J3/16
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