Minimal level sensitive timing representative of a circuit path

摘要

A minimal level sensitive timing representative of a circuit path uses a circuit path timing model to represent a circuit block, which contains multiple circuit paths, in a simplified form, thus reducing the circuit paths to a minimized representation with same timing requirements and fixed clock waveforms. The reduction of the circuit paths in turn results in significant speed-up of static timing analysis (STA) runs on large circuits and reduced memory and storage space requirements. The minimal level sensitive timing representative may simplifies the output from the timing analysis and shortens designer's time to analyze STA results.