| 摘要 |
A differential logic stage includes a precharge circuit, a first evaluate circuit and a second evaluate circuit. The precharge circuit is connected to a first potential and a differential output defined by a first output node and a second output node. The second evaluate circuit is connected to a second potential and a first output node. The second evaluate circuit is connected to the second potential and the second output node. The second evaluate circuit is symmetric with the first evaluate circuit, and in one embodiment each evaluate circuit includes a transistor stack and an input transistor. The transistor stack is connected between the second potential and one of the output nodes. The input transistor is connected in parallel with the transistor stack.
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