发明名称 On-chip testing circuit and method for integrated circuits
摘要 An integrated circuit includes an embedded memory device and an on-chip test circuit. The on-chip test circuit includes a multiplexer and one or more I/O circuits. The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device. As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry. This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit.
申请公布号 US6581174(B2) 申请公布日期 2003.06.17
申请号 US20010944750 申请日期 2001.08.31
申请人 MICRON TECHNOLOGY, INC. 发明人 STUBBS ERIC T.
分类号 G11C29/48;(IPC1-7):G11C29/00;G01R31/28 主分类号 G11C29/48
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