发明名称 Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring
摘要 The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance affect from the approximated Manhattan wiring section is then adjusted with a correction factor. Specifically, the present invention proposes that the capacitance be calculated for an interconnect wiring section by multiplying the length of the interconnect wiring section by an approximated capacitance per unit length value of a similar Manhattan wiring segment and adding a correction factor that corrects for the difference between the approximated Manhattan wiring section and the original non Manhattan wiring section.
申请公布号 US6581198(B1) 申请公布日期 2003.06.17
申请号 US20010681830 申请日期 2001.06.13
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 TEIG STEVEN;CHATTERJEE ARINDAM
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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