发明名称 REFERENCE VOLTAGE GENERATION CIRCUIT IN WHICH OCCURRENCE OF HIGH VOLTAGE WHEN RESET IS PREVENTED
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit in which it is prevented that output reference voltage is made a high potential in a reset period. <P>SOLUTION: A reference voltage generation circuit outputting adjusted reference voltage has a memory element group in which adjusted data can be written, a memory for adjustment having a latch circuit set at reset and set in accordance with adjusted data written in the memory element group, and an amplifier circuit outputting output reference voltage in accordance with adjusted data. This amplifier circuit controls the output reference voltage to the controllable minimum level at reset, and controls the output reference voltage to a level in accordance with the adjusted data after set succeeding to reset. By such constitution, the output reference voltage is controlled to the controllable minimum level in a reset period at applying a power source and at supply of a reset signal from the outside. Therefore, even if this output reference voltage is boosted, generation of boosting voltage destroying internal elements can be prevented. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003168296(A) 申请公布日期 2003.06.13
申请号 JP20010362631 申请日期 2001.11.28
申请人 FUJITSU LTD 发明人 MORI KATSUHIRO
分类号 G11C11/413;G05F3/26;G11C11/407;G11C16/06;H03K19/00;(IPC1-7):G11C16/06 主分类号 G11C11/413
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