| 摘要 |
PROBLEM TO BE SOLVED: To shorten an access time largely by increasing transfer speed of an address signal in a buffer circuit provided in a SRAM macro-cell. SOLUTION: In a SRAM macro-cell 1 provided in a semiconductor integrated circuit device, a clock synchronous circuit 6 is provided at a post stage of input latch circuits 4, 5 to which an address signal is inputted. The clock synchronous circuits 6 consist of NAND circuits 6a, 6b, synchronize with a high level of an internal clock signalϕCK and transfer an address signal. During a low level period of the internal clock signalϕCK, an address signal is a high level output, when the internal clock signalϕCK is transitted to a high level, an address signal of a high level is outputted as it is, only an address signal of a low level is made a high level and transferred. Hence, buffers 7a, 7b may only transfer only a signal of a low level at high speed, increasing determination speed of an address signal Add can be realized. COPYRIGHT: (C)2003,JPO
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