发明名称 SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To improve dispersion of timing of finish of RAS restore operation and start of RAS pre-charge operation in a FCRAM in which a self-timer circuit for determining a RAS restore time (tRAS) of a random cycle time (tRC) and a RAS pre-charge time (tRP) is provided in a ROW system control system. SOLUTION: For example, a signal BNKb is made a 'H' level by an input of a first command. A signal CLKTMRDEF is made a 'L' level 3 clock cycle after input of the command of an internal signal CLKINDRVT based on an external clock signal. Thereby, a signal bBNKTMRb is made a 'L' level. Thereby, the signal BNKb is made a 'L' level. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003168292(A) 申请公布日期 2003.06.13
申请号 JP20020251604 申请日期 2002.08.29
申请人 TOSHIBA CORP 发明人 KAWAGUCHI KAZUAKI;OSHIMA SHIGEO
分类号 G01R31/28;G01R31/3185;G11C7/00;G11C7/10;G11C11/401;G11C11/407;G11C29/12;(IPC1-7):G11C11/407;G01R31/318;G11C29/00 主分类号 G01R31/28
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