发明名称 Programmable logic device and method of controlling clock signal thereof
摘要 An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.
申请公布号 US2003107400(A1) 申请公布日期 2003.06.12
申请号 US20020107073 申请日期 2002.03.28
申请人 FUJITSU LIMITED 发明人 KUMAMOTO NORICHIKA
分类号 H01L21/822;G06F15/80;H01L21/82;H01L27/04;H03K19/177;(IPC1-7):H03K19/173 主分类号 H01L21/822
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