发明名称 |
Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit |
摘要 |
A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits. |
申请公布号 |
US2003110428(A1) |
申请公布日期 |
2003.06.12 |
申请号 |
US20030342651 |
申请日期 |
2003.01.14 |
申请人 |
OCHOA ROLAND;COWAN GREGORY L.;PIERCE KIM M. |
发明人 |
OCHOA ROLAND;COWAN GREGORY L.;PIERCE KIM M. |
分类号 |
G01R31/28;G01R31/3187;G01R31/319;G01R31/3193;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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