Circuit arrangement for clock and data recovery from received signal combines first and second groups of intermediate signals to form combined signals for data and clock recovery

摘要

The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.