发明名称 |
Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes |
摘要 |
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.
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申请公布号 |
US2003108138(A1) |
申请公布日期 |
2003.06.12 |
申请号 |
US20020161922 |
申请日期 |
2002.06.03 |
申请人 |
BUTLER JIM;OTEYZA RAUL |
发明人 |
BUTLER JIM;OTEYZA RAUL |
分类号 |
G06F1/10;H03D3/24;H03K5/00;H03L7/06;H03L7/081;(IPC1-7):H03D3/24 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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