发明名称 Variable voltage tolerant input/output circuit
摘要 A variable voltage tolerant input/output circuit, wherein a leakage current is not produced while having high reliability, characterized in that the circuit includes a clamping circuit for clamping the N-well potential of M1. When the supply voltage VCC is higher than or equal to the input/output voltage VI/O, the N-well potential of M1 is clamped to the supply voltage VCC; when the supply voltage VCC is lower than the input/output voltage VI/O, the N-well potential of M1 is clamped to the input/output voltage VI/O.
申请公布号 US2003107405(A1) 申请公布日期 2003.06.12
申请号 US20020313572 申请日期 2002.12.06
申请人 WANG CHIH-HSIEN 发明人 WANG CHIH-HSIEN
分类号 H01L21/822;H01L21/8234;H01L27/04;H01L27/088;H03K17/08;H03K17/687;H03K19/003;H03K19/0175;H03K19/0948;(IPC1-7):H03K19/017 主分类号 H01L21/822
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