Method for preventing bit line to bit line leakage in memory cell

摘要

A method for preventing bit line to bit line leakage in memory cell is described. In this method, P-implantation is applied to suppress the leakage current induced by the damage, wherein the damage is caused by the etching step for the formation of spacers. The P-implantation step is performed after the etching step, and such a sequence centralizes the implanted ions to prevent them from decreasing the threshold voltage. On the other hand, the P-implantation step is performed after the bit lines annealing step to prevent the implanted ions from being thermally diffused.