INTERNAL INPUT DATA GENERATION CIRCUIT IN SEMICONDUCTOR DEVICE FOR IMPROVING SETUP/HOLD TIME

摘要

PURPOSE: An internal input data generation circuit in a semiconductor device for improving setup/hold time is provided to perform a stable operation by latching doubly input data with the first clock and the second clock as an inverted clock of the first clock. CONSTITUTION: An internal input data generation circuit includes a delay portion(310), the first latch portion(321), the second latch portion(322), and an internal input data generation portion(340). The delay portion delays external data during a predetermined time and outputs input data. The first latch portion is synchronized with the first clock in order to latch the input data and generate the first signal. The second latch portion is synchronized with the second clock in order to latch the input data and generate the second signal. An internal input data generation portion(340) generates the activated internal input data when one signal of the first and the second signals is activated. The first clock is the clock signal delayed by a path. The second clock is an inverted signal of the first clock.