| 摘要 |
A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The register controlled DLL further includes a reset signal generator to generate a reset signal used to initialize the delay locked loop (DLL), a phase comparator to initialize a phase comparison signal in which the phase of a feedback clock signal delayed by a reference clock signal and the delay model is compared and outputted into a predetermined signal by using a comparison enable signal having an inverse phase to that of the reset signal, and a shift register to block an electric current running on a first latch of a plurality of latches with the reset signal during the initialization.
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