| 摘要 |
In a cache memory, a flag register (22, 22') stores flag bits (F0, F1, ...) for showing whether or not regions of a tag memory (11) are faulty. The flag register is accessed by a part (CADD') of a first cache address (CADD) generated from a data processing unit (2). A cache address generating circuit (23, 23') combines the above-mentioned part with outputs of the flag register to generate a second cache address (CADD'') for accessing a tag memory (11). A comparator (14) compares the first cache address with an address read from the tag memory. A data memory accessing circuit (17) accesses the data memory by the first cache address in accordance with whether or not the first cache address coincides with the address read from the tag memory. A determining circuit (15, 21) determines whether the regions of the tag memory are faulty, so that one of the flag bits accessed by the second cache address is adjusted in accordance with whether or not a corresponding one of the regions of the tag memory is faulty. <IMAGE> |
