发明名称 |
TRANSMISSION-GATE BASED FLIP-FLOP |
摘要 |
Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.
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申请公布号 |
US2003107421(A1) |
申请公布日期 |
2003.06.12 |
申请号 |
US20010010046 |
申请日期 |
2001.12.06 |
申请人 |
MARKOVIC DEJAN;TSCHANZ JAMES W.;DE VIVEK K. |
发明人 |
MARKOVIC DEJAN;TSCHANZ JAMES W.;DE VIVEK K. |
分类号 |
H03K3/037;H03K3/356;H03K3/3562;(IPC1-7):H03K3/356 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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